Field of the Invention
The present patent application relates to a method for forming a dielectric zone in a semiconductor substrate.
The electrical performance of integrated passive components such as polysilicon resistances, polysiliconxe2x80x94polysilicon and/or metalxe2x80x94metal capacitances and also coils is often impaired by parasitic capacitive coupling with the semiconductor substrate used. This occurs in particular when semiconductor substrates having a low conductivity are used. The capacitive substrate coupling can lead to a drastic impairment of radio frequency components. In order to decouple the components from the substrate, a dielectric insulating layer may be disposed locally under the components to be insulated. In this case, the thicker the dielectric layer is made, the better the decoupling of the components from the substrate. There are already various possibilities for producing thick insulation layers. In order to insulate inductances that are realized in the topmost metal plane, it is possible to use very thick, organic spin-on layers such as polyamide. However, owing to their temperature sensitivity, these materials can only be used at the end of the process. Furthermore, these layers have the disadvantage that subsequent high-resolution patterning is made more difficult on account of the large layer thickness of approximately 10 xcexcm. Therefore, these layers can only be used for insulating the last metal plane, in which the contact hole openings to underlying layers can be formed without fine patterning and, consequently, occupy a large proportion of the substrate surface.
A further method for decoupling the components from the substrate consists in removing the substrate under the components in a large-area manner. As a result, the components are disposed in a freely suspended manner above the substrate. Although this procedure affords good decoupling, the mechanical stability of the structure is susceptible to disturbances and tends to oscillate. Furthermore, it is difficult to package the circuits in a housing since the freely suspended components should not be damaged.
Furthermore, it is possible to form very thick dielectric layers for example by chemical vapor deposition (CVD) methods or thermal oxidation on the substrate. However, these methods have the disadvantage that they are extremely slow and thus work uneconomically. A further disadvantage is that the thick dielectric layers are not produced locally but rather over the entire wafer. This has the disadvantage that subsequent patterning of the thick layer can only be effected in a coarse fashion and fine patterning is made more difficult. Furthermore, the thick dielectric layer produces an extremely unfavorable topography on the substrate surface, thereby making the subsequent process steps more difficult.
It is accordingly an object of the invention to provide a method for forming a dielectric zone in a semiconductor substrate which overcomes the above-mentioned disadvantages of the prior art methods of this general type, which has an increased thickness and an improved planarity.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for forming a dielectric zone in a region of a semiconductor substrate. The method includes the steps of forming a first trench and a second trench in the region of the semiconductor substrate resulting in a web being formed between the first trench and the second trench; providing a first dielectric layer in the first trench and the second trench; removing the web, a third trench thereby being produced; and providing a second dielectric layer in the third trench.
By way of example, the invention forms the first and the second trench, resulting in a web being produced between the two trenches. If it is envisaged that a relatively large region of the substrate surface is to be provided with a dielectric zone, then, for example, a whole series of trenches with intervening webs are formed. In this case, the trenches can be formed with a depth that corresponds to the subsequent thickness of the dielectric zone. The trenches are then filled with the first dielectric layer, it merely being necessary to deposit a layer thickness that approximately corresponds to half the trench width. This process is fast and very inexpensive in comparison with a thick layer thickness of the dielectric layer. A web between the deposited first dielectric layer is subsequently removed, a first trench thereby being produced. The third trench is formed, for example, with a depth which approximately corresponds to the depth of the previously formed first trench and thus to the filling depth of the first dielectric layer. This makes it possible to fabricate very thick dielectric layers in a semiconductor substrate, the fabrication being realized not by the deposition of correspondingly large layer thicknesses but by the conformal filling of very deep trenches. For filling the trenches, all that is required is a layer thickness that approximately corresponds to half the trench width.
In an advantageous development of the method according to the invention, the first dielectric layer is planarized. This procedure has the advantage that the web between the first and second trenches is uncovered by the planarization step and can be removed in a subsequent etching step. Furthermore, the planarization step has the advantage of avoiding a topological step between the surface of the semiconductor substrate and the dielectric zone.
A further refinement of the method according to the invention provides for the web to be removed by isotropic or by anisotropic etching. Since the web is disposed between two trenches filled with a dielectric material, the web can be etched by isotropic etching that selectively removes the web with respect to the dielectric layer in the first and second trenches. Anisotropic etching is likewise possible, which uses reactive ion etching, for example, and is selective with respect to a resist mask, with respect to a hard mask or with respect to the material difference between web and dielectric layer.
Furthermore, it is provided that a hard mask is used for forming the first trench. The use of a hard mask has the advantage that the first trench and/or the second trench can be formed with a large trench depth.
Furthermore, it is provided that a resist mask is used for forming the third trench. The resist mask may serve during isotropic etching, for example, for uncovering a window in which the web is disposed, so that the rest of the substrate is protected from the etching.
A further refinement of the method according to the invention provides for the first dielectric layer to be formed in an upper region of the first trench and a cavity to be produced in a lower region that is disposed below the upper region. The cavity has the advantage that improved decoupling between the substrate and the component is achieved.
Furthermore, it is provided that the second dielectric layer is formed in an upper region of the third trench and a second cavity is produced in a lower region that is disposed below the upper region. The second cavity has the advantage that the decoupling between the substrate and the component is improved further.
Furthermore, it is provided that the first cavity and the second cavity are formed in a contiguous manner. The contiguous formation of the first and the second cavities has the advantage that improved decoupling between the substrate and a component disposed on the dielectric zone is achieved.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for forming a dielectric zone in a semiconductor substrate, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.